1. Field of the Invention
This invention relates to the field of operational amplifier input stages, and particularly to methods of preventing phase inversion for a cascoded transistor op amp input stage.
2. Description of the Related Art
A basic op amp input stage is shown in FIG. 1. A differential pair MN1 and MN2 have their sources connected to a common mode node 10, their gates connected to receive a differential input signal (Vxe2x88x92 and V+), and their drains connected to a load 12 (here, a pair of resistors). A tail current Itail is connected at common mode node 10. MN1 and MN2 conduct respective currents through load 12 in response to the input signal, which creates an output voltage Vout.
An op amp input stage has an associated common mode input range. For example, for FET and MOSFET input transistors, the common mode input range is defined as the voltage range over which the input devices are in the pinch-off region. For an N-channel FET, this condition is met when the FET""s drain-source voltage Vds is greater than Vgsxe2x88x92Vp, where Vgs is the FET""s gate-source voltage and Vp is its pinch-off voltage.
There is an intrinsic diode (D1, D2) present between the gate and drain of each input FET (or, for a bipolar input stage, between the base and collector of each input transistor). Normally, the drain voltage of an input FET decreases with a rising input. However, if the gate voltage Vg of an input FET exceeds its drain voltage Vd, the input stage is no longer within its common mode input range. If Vg becomes sufficiently greater than Vd, the intrinsic diode becomes forward-biased, such that a condition known as xe2x80x9cphase inversionxe2x80x9d occurs. When in this condition, a rising input at the gate of an input FET causes the voltage at its drain to increase, rather than decrease as it would normally. Phase inversion also causes the entire tail current Itail to be drawn through the input terminals.
Phase inversion can easily occur in a folded cascode input stage, in which cascode transistors are inserted in series with the drains of respective input transistors (assuming a FET input stage). The cascode transistors are driven with a cascode voltage, which is typically arranged to float with the common mode input voltage Vcm[=(V++Vxe2x88x92)/2]. If Vcm gets too high, the transistor which creates the cascode voltage saturates, fixing the cascode voltage and thereby pinning the input FETs"" drain voltages. When so pinned, the intrinsic diode of one of the input FETs can eventually become forward-biased, and phase inversion occurs.
A phase inversion prevention circuit for an operational amplifier input stage is presented, which overcomes the problems noted above.
The present phase inversion prevention circuit includes primary and secondary input pairs, and a detection circuit which detects when either of the primary input pairs"" intrinsic diodes is near a forward-biased condition. When such a condition is detected, a switching network switches tail current from the primary input pair to the secondary input pair, which takes over the input stage""s amplifying duties.
The invention is particularly suitable to use with folded cascode input stages, which are especially susceptible to phase inversion. In such applications, the detection circuit detects the onset of phase inversion by monitoring the which drives the cascode transistors. The outputs of the secondary input pair are connected to bypass the cascode transistors. Thus, when the onset of phase inversion is detected, the switching network operates to disable the primary input pair and enable the secondary input pair; with the cascode transistors bypassed, the secondary input pair avoids phase inversion.
Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings.